The present invention relates to a method for fabricating a SOI (Semiconductor on Insulator) type semiconductor device, and more precisely, relates to a method for forming a connection to a buried layer of a semiconductor device fabricated by SOI technology.
In SOI technology, a number of semiconductor single crystalline layers having the width and length in the order of from a few tens to hundreds of microns, for example, are formed on an insulating layer and then a functional device, such as a transistor or diode, is fabricated in each of the single crystalline layers. SOI technology is expected as a breakthrough in future LSI (large scale integration) circuits for the existing speed and packing density limitations. That is, since each of the semiconductor single crystalline layers is usually formed so as to be embedded in an insulating matrix having a depth of a few tens of a micron, the transistor or diode fabricated in each single crystalline layer is dielectrically isolated from the others and also from the substrate, such as silicon; therefore, the semiconductor device has low stray capacity and high breakdown voltage characteristics.
The single crystalline layers are originally formed by recrystallizing a polycrystalline layer, such as a polysolicon layer, which has a thickness in the order of microns, and which is deposited on an insulating layer, such as a silicon dioxide layer. The polycrystalline layer is passivated except the regions at which the final single crystalline layer is formed. The regions are also referred to as "device regions" hereinafter. There are various cases wherein the passivation is performed prior to or after the recrystallization, and the recrystallization is performed entirely or partially of the polycrystalline layer. Thus, the islands of single crystalline layers floating in an insulating matrix are obtained. An epitaxial layer is then formed on each of the recrystallized layers by using an ordinary epitaxial growth technique, such as chemical vapor deposition (CVD), if necessary.
A SOI type semiconductor device of the type described above is also referred to as a dielectrically isolated integrated circuit. If the insulating layer and the single crystalline layer thereon are formed on a substrate wherein transistors or diodes are fabricated in advance, a three-dimensional integrated circuit is possible. The three-dimensional structure can be extended further, if another stack of an insulating layer and semiconductor single crystalline layers is formed on the present stack of the insulating layer and the single crystalline layers.
Various methods and results of fabricating such semiconductor single crystalline layers and prototype SOI semiconductor devices, including three-dimensional integrated circuits, have been disclosed in several reports. Such reports include "Recrystallization of Si on Amorphous Substrates by Doughnut-Shaped Cw Ar Laser Beam" by S. Kawamura et al., Appl. Phys. Lett. 40(5), 1 Mar. 1982, and "Three-Dimensional CMOS IC's Fabricated by Using Beam Recrystallization" by S. Kawamura et al., IEEE ED Letters, Vol. EDL-4, No. 10, Oct. 1983.
As in the ordinary bipolar integrated circuits directly formed on a silicon substrate, a highly doped buried layer to reduce collector resistivity is required and provided for the transistor in the SOI type semiconductor device using general bipolar technology. The buried layer is formed in the original single crystalline layer (i.e., the recrystallized layer), and the functional device, such as the transistor, is fabricated in the epitaxial layer grown on the recrystallized layer. There has been no disclosure concerning the fabrication of the buried layer of a SOI type semiconductor device because the prior art SOI type bipolar semiconductor devices are based mainly on a so-called lateral bipolar technology, wherein the resistivity of the collector region is not a serious problem. For example, see "Fully Isolated Lateral Bipolar-MOS Transistors Fabricated in Zone-Melting-Recrystallized Si Films on SiO.sub.2 " by B-Y. Tsaur et al., IEEE ED Letters, Vol. EDL-4, No. 8, Aug. 1983.